1. Field of the Invention
The present invention relates to a method for forming a field effect transistor upon a semiconductor substrate in a fashion whereby the completed transistor does not exhibit mask edge detects adjoining its gate spacer oxides. More particularly, the present invention relates to a method for forming a smooth topographic transition between the gate spacer oxides of a field effect transistor and the semiconductor substrate adjoining those gate spacer oxides, so that mask edge detects are not produced at regions adjoining the gate spacer oxides when amorphous source/drain electrodes of the transistor are annealed.
2. Description of Related Art
With the advent of advanced generations of semiconductor transistor technology, such as Very Large Scale Integrated (VLSI) circuit technology and Ultra Large Scale Integrated (ULSI) circuit technology, there is a substantial and continuing interest in understanding the sources and control of detects which contribute to semiconductor functionality and reliability losses. Such detects may arise from several sources. Typical defect sources include semiconductor manufacturing environments, manufacturing processes, process tooling and materials.
With regard to detects whose sources derive from manufacturing processes and materials, it is well known in the art that several types of defects may be formed through the process of implanting dopant ions into semiconductor substrates to form active semiconductor regions. It is also well known that the high ion implant doses required for formation of many advanced semiconductor circuit components simultaneously make amorphous the crystalline silicon semiconductor substrate into which the dopant ions are implanted. Upon subsequent annealing to recrystallize the amorphous region, latent defects are formed or appear at locations within or adjoining the recrystallized region.
Defects which are incident to annealing and recrystallization of amorphous ion implanted semiconductor substrates fall into three categories. The first two categories are Projected Range Defects (PRDs) and End of Range Detects (ERDs) These defects appear as dislocations within the depth of a semiconductor substrate which has been ion implanted and recrystallized. The location and density of these defects derives from the intensity and dose of the implanting ions which caused the initial crystalline to amorphous transition of the semiconductor substrate.
The third category of detect related to recrystallization of a silicon semiconductor substrate made amorphous through ion implantation is the Mask Edge Detects (MEDs). In contrast to PRDs and ERDs, MEDs are defects typically localized to the surface of the recrystallized semiconductor substrate. In particular, MEDs are formed at locations where a recrystallizing silicon substrate surface adjoins another structure on the surface of the silicon substrate. A common structure adjoining which an MED may be formed is a gate spacer oxide structure. Gate spacer oxides are formed to insulate the gate electrode edge surfaces from the adjoining source/drain electrodes in field effect transistor structures. When formed in this location, an MED is commonly referred to as a gate spacer MED. It is towards the elimination of these gate spacer MEDs that the present invention is directed.
A second type of semiconductor fabrication defect which is nominally unrelated to defects associated with ion implantation processes is parasitic current leakage between polysilicon gate electrodes and source/drain electrodes upon which electrodes have been formed metal salicide layers. A metal salicide layer is a metal silicide layer which is formed in a self aligned fashion. Such parasitic leakage is known to occur due to encroachment of the salicide layers upon the surfaces of semiconductor structures which separate the polysilicon gate electrode and the source/drain electrodes. The reduction in magnitude of this parasitic leakage current, either in conjunction or independent of elimination of gate spacer MEDs, is a desirable goal in light at the shrinking physical dimensions of advanced semiconductor devices.
Schematic diagrams which illustrate the formation of gate spacer MEDs and metal salicide layer encroachment within field effect transistor device structures are shown in FIG. 1a, FIG. 1b, FIG. 2a and FIG. 2b. The formation of gate spacer MEDs is shown in FIG. 1a and FIG. 1b. FIG. 1a shows a cross-sectional diagram of a field effect transistor at a point in its processing where a high dose ion implant has been made into the semiconductor substrate for the purpose of establishing the source/drain electrodes of the semiconductor device. As is common in advanced semiconductor devices, the ion implant was of sufficient dose to make amorphous the silicon semiconductor substrate into which it was implanted.
In FIG. 1a, a semiconductor substrate 10 has formed upon its surface a gate electrode 12 which is separated from the semiconductor substrate 10 by a gate oxide 14. On both sides of the gate electrode 12 are formed gate spacer oxides 16 which insulate the gate electrode 12 from source/drain electrodes 18. Also formed within the surface of the semiconductor substrate 10 are low dose ion implants 20, which are of sufficiently low dose that the semiconductor substrate 10 regions into which they are implanted remain crystalline.
The purpose of the low dose ion implants 20 is to reduce the peak electric field within the semiconductor substrate 10 such that electrons within the semiconductor substrate 10 are not injected into the gate oxide 14. The use of low dose ion implants 20 implants becomes more important as transistor device dimensions are reduced while maintaining constant supply voltages. Adjoining the low dose ion implants 20 are high dose ion implanted regions which form the source/drain electrodes 18. The dose of the high dose ion implant is sufficient to make amorphous the source/drain electrodes 18.
FIG. 1b shows the same cross-sectional diagram as shown in FIG. 1a after the semiconductor structure has been annealed to recrystallize the amorphous source/drain electrodes 18. As the amorphous semiconductor regions recrystallize, the recrystallization interface advances towards: (1) the edges of the gate spacer oxides 16, and (2) the interfaces with the low dose ion implants 20. At these interfaces, gate spacer MEDs 22 are formed. The gate spacer MEDs 22 are manifested as cracks through the semiconductor substrate 10 at its juncture with the gate spacer oxides 16. The gate spacer MEDs 22 may be accompanied by additional secondary and tertiary detects. These additional defects and dislocations, if formed, are often localized to the area of the semiconductor substrate beneath the gate oxide 14.
Correlating with FIG. 1a and FIG. 1b are FIG. 2a and FIG. 2b. FIG. 2a shows a cross-sectional schematic diagram equivalent to the diagram of FIG. 1a with a significant limitation and a related exception. The limitation is that the gate electrode 12 of FIG. 1a is now a polysilicon gate electrode 13. The related exception is that a metal layer 24 has been deposited over the surface of the entire semiconductor structure. The metal deposited in the metal layer 24 is chosen such that it will form a metal salicide upon sintering with silicon surfaces which it contacts. Metals which are known to form such salicides include but are not limited to cobalt, tantalum, platinum, tungsten and titanium.
FIG. 2b shows a cross-sectional diagram of the semiconductor structure shown in FIG. 2a after the simultaneous annealing to recrystallize the amorphous ion implanted source/drain electrodes 18 and sintering to form metal salicide layers on silicon surfaces contacted by the metal layer 24 of FIG. 2a. Unreacted portions of the metal layer 24 of FIG. 2a are absent from FIG. 2b. They may be removed through a selective etch process appropriate to the metal from which is formed metal layer 24.
Analogously to FIG. 1b, FIG. 2b also shows gate spacer MEDs 22 which are formed upon recrystallization of source/drain electrodes 18. Also shown in FIG. 2b are a gate electrode metal salicide layer 26 and a pair of source/drain electrode metal salicide layers 28. Shown in FIG. 2b are the overhangs of the gate electrode metal salicide layer 26 onto the tops of the gate spacer oxides 16 and the encroachment of the source/drain electrode metal salicide layers 28 onto the vertical edges of the gate spacer oxides 16. The overhangs and encroachments, if pronounced, may lead to parasitic leakage currents between the polysilicon gate electrode 13 and the source/drain electrodes 18. The reduction of these parasitic effects is a desirable feature for advanced field effect transistors.
The presence and the mechanism of formation of MEDs has been discussed in the art. For example, Tsui, et al., "Impact of Structure Enhanced Detects Multiplication on Junction Leakage," Technical Digest of the International Reliability Physics Symposium 383 (1994), discusses junction leakage due to MEDs and dislocations associated with polysilicon layers on field oxide (FOX) structures within semiconductor substrates. Modification of various process parameters, including implantation dosage, screen oxide parameters and post-implant annealing parameters were shown to slightly suppress, but not eliminate, the leakage current.
More pertinent to the present invention, however, is the disclosure by Horiuchi, et al., "Gate Edge Effects on SPE Regrowth From As+ Implanted Si," Nuclear Instrumentation Methods in Physics Research B37/38 285 (1989). Within that disclosure, Horiuchi et al. discuss the strong dependence of MEDs upon the geometry of the amorphous implanted area beneath a gate edge. The presence of MEDs was found to depend little on gate material, but substantially upon substrate orientation with respect to gate direction. Based upon these observations, Horiuchi, et al. suggest methods to eliminate MEDs which involve: (1) geometric considerations of masking layers with regard to substrate orientation, and (2) kinetics of amorphous substrate recrystallization as related substrate orientation.
Absent from the prior art is the suggestion that modifications to semiconductor substrate topography may play a significant role in eliminating gate spacer MEDs. Also absent from the prior art is the suggestion that inventions directed towards eliminating gate spacer MEDs may consequentially also reduce parasitic leakage in field effect transistors upon whose electrodes are formed metal salicide layers.